`include "../rtl/defines.v"
module if_id(
           input wire clk,
           input wire rst,
           input wire [31: 0] inst_i,
           input wire [31: 0] inst_addr_i,
           input wire hold_flag_i,

           output wire [31: 0] inst_addr_o,
           output wire [31: 0] inst_o
       );

// 将指令和指令地址打一拍

reg rom_flag;

always@(posedge clk)
	begin
		if (!rst | hold_flag_i)
			rom_flag <= 1'b0;
		else
			rom_flag <= 1'b1;
	end
// 已经在rom中打了一拍了
assign inst_o = rom_flag ? inst_i : `INST_NOP;

// dff_set#(
//            .DW ( 32 )
//        )dff1(
//            .clk ( clk ),
//            .rst ( rst ),
//            .hold_flag_i(hold_flag_i),
//            .set_data ( `INST_NOP ),
//            .data_i ( inst_i ),
//            .data_o ( inst_o )
//        );

dff_set#(
           .DW ( 32 )
       )u_dff_set(
           .clk ( clk ),
           .rst ( rst ),
           .hold_flag_i(hold_flag_i),
           .set_data ( 32'd0 ),
           .data_i ( inst_addr_i ),
           .data_o ( inst_addr_o )
       );



endmodule
